1. Field of the Invention
This invention relates to systems for the debugging of digital electronic systems and, more specifically, to a system for optimal scheduling of logic simulators used in such debugging.
2. Discussion of the Related Art
In debugging new digital electronic circuit designs, it is common to use circuit simulations to test for errors in the design. Such simulations may be implemented as computer programs running on a general-purpose computer, or as special hardware-software combinations intended for simulating digital systems. The term "simulator" as used herein denominates any of a range of software and hardware assemblies as well as the circuit prototype itself.
Different types of simulators are often used at different stages of the design process. As the design debugging progresses, hardware typically replaces software and mixed hardware-software simulators yield eventually to the design prototype itself. This is necessary because each simulator differs in speed, in available range of identifiable errors, and in ease of modification required to incorporate a design revision or "fix" for a design error or "bug". They also differ in ease of finding a bug because the software simulator provides internal logic signals while the hardware chip is limited to actual inputs and outputs. For example, a software simulator may cycle millions of times more slowly than the equivalent hardware prototype but can be modified merely by editing a file on a computer screen in a few minutes. Fixing the same bug in a full-speed hardware prototype requires refabricating a new version of an integrated circuit, a process that can take weeks. Likewise, two software simulators may differ considerably in cycle speed and range of detectable errors if, for example, one simulates signal timing and the other does not.
In scheduling a debug strategy for a new digital system design, the "cutover" points must be established for moving from a slower, "soft" simulator to a faster, "hard" simulator. This decision may be complicated when the scheduled simulators are shared among several projects.
Although the estimation of the number of bugs (design errors) in a digital circuit design is a well-known procedure that considers the size and complexity of the design, there is no equivalently formal method known in the art for establishing the cutover point from one simulator to the next. The cutover is typically accomplished on an ad hoc basis, determined by the designer's intuition and unrelated production schedules. The release of the design and commitment to hardware prototyping normally results from exhaustion of available test data, "gut-feel" or production schedules arising from marketplace forces.
Thus, the designer has no available formal method for advance scheduling of circuit design simulation resources and cutover points. This is a clearly felt need in the art. The circuit designer is often left without formal grounds for continuing the debug simulation at a certain level when confronted by management imperatives to "push ahead" to hardware prototyping. Without formal means for optimal cutover to prototyping, the first prototype often incorporates more design errors that would otherwise be found after "adequate" debugging in "soft" simulators. This increases costs for everybody concerned, as do unnecessary prototyping delays arising from overcaution.
Practitioners in the art have often proposed systems for improving logic circuit design efficiency. For instance, in U.S. Pat. No. 4,801,870, Edward B. Eichelberger, et al disclose a statistically optimal pattern testing method for quality control of production circuits after completion of debugging. They teach a shortcut to the production circuit one-hundred-percent input pattern testing procedure that employs a weighted random pattern input testing technique. However, Eichelberger, et al neither consider nor suggest methods for optimal cutover from software to hardware simulation during debugging of the initial circuit design. In German Patent DE 32 25 811, Professor Huang, et al disclose a system for predicting the complete performance, timing and regulation of a process configured as a general purpose n.sup.th order model. Their system provides a sophisticated modeling technique that may be useful for software simulation and debugging but Huang, et al neither consider nor suggest how to predict the cutover point from software to hardware simulation. Similarly, in U.S. Pat. No. 5,053,980, Kiyoshi Kanazawa discloses a system for increasing the speed of a software logic simulator that relies on introducing a new event identifier technique that avoids the event-driven simulation delays that result from the normal requirement that all events terminate before the simulation clock is incremented. Again, Kanazawa teaches a useful method for software simulation but neither considers nor suggests a formal technique for cutting over from software to hardware simulation during circuit design debugging.
More to the point, M. J. Campion, et al ("Functional Testing Index", IBM Technical Disclosure Bulletin, Vol. 23, No. 3, p. 985, August 1980) briefly suggest a method for formally calculating how much functional testing has already been performed in a simulated data processor design. Campion, et al suggest an "after-the-fact" modeling technique for formally measuring the progress of software simulation but neither consider nor suggest a method for predictively scheduling cutover from software to hardware simulation in a debugging process.
Thus, there is a clearly-felt need for a system that can optimally schedule the cutover or transition between two or more design simulators during debugging in accordance with explicit and fixed (formal) rules. The related unresolved problems and deficiencies are clearly felt in the art and are solved by this invention in the manner described below.